New Programming Solution Redefines Reconfigurable Computing Market Previously
Lacking Standard C Tools; 'Virtual Reconfigurable ASICs' Can Be Implemented In
Minutes With C as Opposed to Man-Years in Verilog and Integrated With Any DSP
Or CPU
SAN JOSE, Calif., March 12 /PRNewswire/ -- PACT XPP Technologies, Inc.,
the world leader in the development of reconfigurable parallel coprocessor
cores and solutions, today announced immediate availability of the company's
new XPP(TM) Vectorizing C-Compiler (XPP-VC) technology. This is the first
solution allowing a developer to easily create 'virtual ASICs' using the C
language as opposed to laborious hardware programming in Verilog(R) or using
the proprietary tools that have characterized parallel programming to date.
For the first time it is now possible to migrate to reconfigurable
technologies with minimal programming effort while maintaining the use of
existing codebases -- all made possible through XPP-VC. PACT XPP will be
demonstrating XPP-VC at the Embedded Systems Conference in San Francisco from
3/13/02 - 3/15/02 (Booth 5260, North Hall).
In addition, the company also announced immediate availability of a new
version of the PACT XDS Development Suite, which consists of an automatic
mapper, placer and router for the company's XPP cores, a clock accurate
software simulator for testing and simulation of programs for a selected core
and a new graphical visualization tool.
The visualization tool is available as a free download from
http://www.pactcorp.com -- further technical details on the XDS Development
Suite and XPP-VC may also be obtained from this site.
Using PACT's massively parallel, reconfigurable XPP cores as an
'algorithmic coprocessor' in tandem with a standard DSP or RISC CPU typically
enables a ten-fold increase in performance, using less than 10% of the power
draw of leading DSP designs. PACT's XPP core processes data at rates of up to
50,000 MIPS.
"Through the combination of our unique C-compiler with the XDS Development
Suite, we have removed the final obstacle preventing reconfigurable computing
from becoming a mainstream technology within SoC designs. The longstanding
dream of easily designing 'programmable ASICs' is now a reality through PACT's
unique combination of reconfigurable coprocessor cores with the ubiquity of
C," said Martin Vorbach, CTO of PACT. "XPP-VC transparently allows the reuse
of existing sequential C-code for parallel execution on the XPP array,
allowing programmers to easily port their existing DSP software to the XPP
parallel architecture."
Faster Time to Market Using C
The new compiler technology extracts code that has been annotated by the
programmer for processing on the XPP core and automatically generates
supplementary interface code between the DSP/CPU code and the XPP code.
XPP-VC can generate binaries for both XPP and C-code for any supported host by
the main compiler it is integrated into.
XPP-VC is intended for integration with a complete ANSI C-compiler, such
as GNU C or others, and is designed for deployment on a hybrid RISC/XPP or
DSP/XPP system. However, it can also be used as a standalone compiler for XPP
cores (currently the world's highest-performance 32-bit architecture).
Using XPP-VC, new designs can be implemented in minutes for testing and
implementation -- for example, creating a single-purpose (and expensive to
produce) edge-detection ASIC for imaging applications in Verilog can take up
to 2 man-years. Using PACT's new C technology, it can be programmed in under
15 minutes with less than 20 lines of code and with full ASIC-level
performance. In addition, the virtual ASIC is fully reconfigurable/deletable
and capable of running in multiple, parallel instances on the PACT core.
XPP-VC Features
-- High-level language programming: XPP-VC allows developers to program
the massively parallel XPP cores just like conventional processors,
using ANSI C, the industry-leading sequential software language.
-- Data dependence analysis: inherent program parallelism is
automatically detected to increase application performance.
-- Loop vectorization: Operator pipelines are generated for suitable
loops. Pipeline balancing ensures optimum throughput.
-- Memory address generation: C array accesses are translated into
accesses to XPP internal RAMs or external memory.
-- Run-time reconfiguration: Subsequent configurations are rapidly
configured and executed on the XPP core, supported by the configuration
management hardware.
-- I/O access functions: For stand-alone compilation, access to the ports
is provided by specialized XPP input/output functions.
XPP Core Capabilities
XPP is deployed as a licensable IP (Intellectual Property) core for
incorporation within SOC or DSP designs used in markets such as 2.5G+ base
stations, mobile telephones and other devices requiring fully reconfigurable,
massively parallel processing capabilities with minimum power requirements and
maximum scalability.
XPP utilizes a highly parallel 'virtual ASIC' array of PAEs (Processing
Array Elements, made up of individual Arithmetic Logic Units) that can be
reconfigured on the fly, erased and rebuilt with virtually zero latency.
These virtual ASICs can also execute, be modified, or erased fully in parallel
of one another, or even with data interchange, across the array -- all the
while being fully controlled via a unique configuration manager that insulates
timing and data-dependency issues from the programmer or designer.
The core is tailored to meet the exponentially growing demands for
bandwidth and performance: benchmarks on the company's XPU-128 sample chip
have proven it to be the world's highest-performance 32-bit design. The core
enables efficient reconfiguration strategies, which can be performed in
parallel for the processing of data to achieve the highest possible
application performance -- equal to 50,000 MIPS or the equivalent of
80 Pentium(R) 4 chips running in parallel at 1.3 GHz, based on the initial
100 MHz clock speed of the core.
Using the LSI Logic (Milpitas, CA) .18um ASIC Library has enabled PACT to
increase the clock speed of the core by 33% to 150 MHz+, while simultaneously
reducing the die size requirements for each individual PAE in the XPP core.
The power consumption for typical DSP algorithms running on XPP is between
0.15W and 1.5W at the new clock frequency of 150 MHz. Using less than 10% of
the power draw of leading DSP designs, XPP enables new benchmarks of
flexibility and performance in silicon/software design and implementation.
Pricing & Availability
XPP-VC and the XDS Development Suite are available immediately. Both are
available for a thirty-day free evaluation and may be obtained at
http://www.pactcorp.com or by contacting sales@pactcorp.com. Cost for the
full suite including both products is $20,000 US -- the visualization tool is
available at no charge as a separate download.
About PACT
PACT XPP Technologies (San Jose, CA) is a semiconductor and intellectual
property vendor that has developed a unique, wave-reconfigurable architecture
that combines the performance of an ASIC with the flexibility of a DSP. PACT
has developed the world's most powerful 32-bit processor core as a first
implementation on the company's eXtreme Processor Platform (XPP(TM)), which
has demonstrated performance up to 50X greater than conventional sequential
processors and 20X higher than DSPs. PACT provides XPP cores that can be
easily tailored for next-generation mobile telephones, base stations,
workstations and other high-performance devices.
More information about PACT XPP is available at http://www.pactcorp.com,
including a number of detailed white papers on the company's technology.
NOTE: XPU and XPP are trademarks or registered trademarks of PACT
Gmbh -- all other trademarks and registered trademarks previously cited herein
are hereby acknowledged.
SOURCE PACT XPP Technologies, Inc.
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Related links:
http://www.pactcorp.com
CONTACT:
Ron Mabry of PACT XPP Technologies,
+1-408-392-3756, or ron.mabry@pactcorp.com, or Gunther Zeisel of
PACT XPP (Europe), +011-49-89- 353-44-221, or
guenter.zeisel@pactcorp.com; or Jonathan Hirshon of Horizon
Communications, +1-408-969-4888, ext. 101, or jh@horizonpr.com,
for PACT XPP Technologies
NOTE TO EDITORS: Detailed whitepapers, executive photos and other
data may be found at the Horizon Communications website at
http://www.horizonpr.com
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