SAN JOSE, Calif., May 10 /PRNewswire/ -- Scaling of semiconductor
circuit features to ever-smaller dimensions is essential to keeping pace
with the International Technology Roadmap for Semiconductors (ITRS) and
adhering to Moore's Law. The industry will learn about solutions to these
and other hot-button issues at the Challenges in Device Scaling TechXPOT,
which will be held during SEMICON West 2006, July 11-13 at the Moscone
Center in San Francisco.
Maintaining the "show-within-the-show" concept, the Challenges in
Device Scaling TechXPOT offers targeted content and sessions focusing on
the equipment and materials challenges facing the semiconductor industry,
as it develops the devices and processes necessary for the 45 and 32nm ITRS
nodes. The Challenges in Device Scaling TechXPOT will be located in the
North Hall of the Moscone Center.
"The intent of the TechXPOTs in general, is to bring highly focused and
relevant content to SEMICON West attendees," said Ralph Kirk, technical
director of North America Programs at SEMI. "By segmenting SEMICON West
into technical focus areas, we are creating dedicated locations that
highlight similar innovative technologies, thereby allowing attendees to
make more efficient use of their time at the expo."
The area will feature sessions focusing on a range of topics including
mask challenges, featuring Brian Grenon of Grenon Consulting, Inc.;
engineered substrates, featuring Mayank Bulsara, president of Atlas
Technology; and interconnects and processes for advanced devices, featuring
Ken Monnig, former associate director of Interconnect at International
SEMATECH. SEMI will co-sponsor the DNS Lithography Breakfast Forum as a
Device Scaling TechXPOT satellite session. The event will take place at
7:30 a.m., Wednesday, July 12 at the San Francisco Marriott, and will
feature George Petricich, vice president of product marketing at DNS
Electronics as the Session Chair.
The final sessions will deal with advanced metrology, one focusing on
tools needed to support advances in lithography, chaired by Stephen
Knight., director of the Electronics and Electrical Engineering Laboratory,
Office of Microelectronics Programs at NIST and the second focusing on
tools for identifying defects, and characterizing thin films.
"There are many challenges to realizing 45 and 32 nm processing
technologies," said Kirk. "Visitors to the Device Scaling TechXPOT will
learn about, and further explore these issues, and then, they can speak
directly with the people who are developing the solutions."
TIS 2006 winners in from the Device Scaling TechXPOT will present on
the Manufacturing Productivity & Effectiveness TechXPOT stage in the
Esplanade. Companies selected for products dealing with front-end
processing include: Accretech, Actinix, Advanced Electron Beams, Inc.,
Cabot Microelectronics, Digmesa, Filmetrics, Inc., Metrosol, Inc.,
MultiMetrixs, LLC, Neocera, Inc. and RASIRC.
For more information about the Challenges in Device Scaling TechXPOT,
as well as SEMICON West 2006, please visit http://www.semi.org/semiconwest.
SEMI is a global industry association serving companies that provide
equipment, materials and services used to manufacture semiconductors,
displays, nano-scaled structures, micro-electromechanical systems (MEMS)
and related technologies. SEMI maintains offices in Austin, Beijing,
Brussels, Hsinchu, Moscow, San Jose (California), Seoul, Shanghai,
Singapore, Tokyo and Washington, D.C. For more information, visit
http://www.semi.org.
SOURCE SEMI
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Related links:
http://www.semi.org
CONTACT:
Scott Smith of SEMI, +1-408-943-7957, or
ssmith@semi.org
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