Array of In-Depth Technical Sessions, Business-Focused Events Selected From
Record Number of Submissions
BOULDER, Colo., April 5 /PRNewswire/ -- The 41st Design Automation
Conference (DAC) today announced a strong technical program along with an
expanded number of business-related sessions for its annual conference to be
held June 7-9 at the San Diego Convention Center, San Diego. In addition to
its traditionally diverse and expansive program, this year's new elements
include more than a dozen DAC Pavilion panels, and a new track focused on the
intersection of business and technology issues called "Business Day at DAC."
"This year's program drew from a record 785 paper submissions to create a
conference of the highest quality," said Sharad Malik, 41st DAC general chair.
"Our program builds on past excellence to offer everyone in the industry --
from developers to executives to designers and management -- an even greater
opportunity to learn and experience the latest trends, tools and design
methodologies in electronic design."
More than 10,000 participants are expected to attend this year's
conference, which will showcase more than 170 exhibiting companies and over
200 papers, panels, sessions and tutorials. The conference also will feature
two keynote addresses from recognized industry leaders: Pat Gelsinger, Chief
Technology Officer and Senior Vice President of Intel Corp., and Walden
(Wally) C. Rhines, Chairman of the EDA Consortium and Chief Executive Officer
(CEO) of Mentor Graphics Corporation.
Comprehensive Technical Program
The technical program at the 41st DAC covers a rich assortment of topics
and design challenges. Overall, seven different tracks are included in the
technical program this year: Business; System Level Design and Verification;
Power; Logic Design and Test; Embedded Systems; Nanometer Analysis and
Simulation; and Physical Circuit Design.
* In the System Level Design and Verification Track, the hot topic is
the tightening connection and convergence between system-level design
and physical design -- especially for cutting-edge designs such as
multiprocessor systems on chip (SoCs).
* The Power Track will focus on innovative solutions proposed to address
power issues and overcome the growing leakage problem. The program
will feature specialized power reduction techniques for applications
ranging from microprocessor to multimedia real-time designs.
* Exciting approaches in logic synthesis are the focus in the Logic
Design and Test Track -- techniques like pipelining and retiming that
were traditionally applied to logic gates are now used to optimize
wires. Logic optimizations are extended to handle quantum logic and
reversible circuits. As for test, the program will discuss new
techniques to minimize the power consumed by test logic and methods to
more accurately test power.
* In the Nanometer Analysis and Simulation Track, the challenge of
design for manufacturability is gaining focus and the track will
showcase many innovative ideas to ease this growing problem at all
design stages.
* The sessions in the Physical and Circuit Design Track reflect the
growing importance of analog design in typical state-of-the-art SoCs.
Synthesis and simulation of mixed-signal circuits are hot topics this
year too.
DAC's full-day tutorials occur on two days this year. Monday's tutorial
is titled, "Getting Your 'Cool ASIC' Up to Speed: Practical Techniques and
Tools to Achieve Custom-Like Performance in a Power-Aware Design Flow."
Friday offers five full-day tutorials, including: "Automated Macromodelling
Techniques for Design of Complex Analog, Mixed-Signal Integrated Systems";
"Buffering Interconnect: From Basics to Breakthroughs"; "SystemVerilog for
Verification: The Unification of Design, Testbench and Assertions in a Single
Language"; "Linux for Real-Time and Embedded Systems"; and "Silicon Debug."
Increased Focus on Business
To encourage more exchange on business and technology issues, DAC is
enlarging its business track by adding "Business Day @ DAC" that offers a
full-day to keynotes, panels and special presentations from experts on
business topics that affect technology decisions and directions.
One business special session, "Competitive Strategies in the Electronics
Industry," will explore topics on increasing competitive edge, such as
globalization, patent portfolio management, and strategic marketing. Another,
"Business Models in IP, Software Licensing, and Services," will focus on the
pros and cons of various models used for achieving success, such as the
tradeoffs and interaction between IP and EDA, software license models, and
design and EDA services.
In addition, DAC is offering a line-up of panels and presentations in the
DAC Pavilion on the Exhibitor Floor. The DAC Pavilion sessions are open to
all attendees and feature provocative technical, business and strategy
discussions. The pavilion program will be kicked off Monday morning with "EDA
Business Forecast" featuring Gary Smith, chief analyst at Gartner Dataquest.
A sample of some the 13 other pavilion events include such stimulating topics
as:
* User Forums or Useless Forums?
* EDA Mergers & Acquisitions: Glory or Death?
* Export Controls in the Age of Globalization
* Ask the CTOs: Everything You Wanted to Know But Were Afraid to Ask
* ASIC, FPGA or SoC: Which Should Your Next Chip Be?
The attached addendum provides more detail on conference highlights. For
more information on this year's technical program also visit DAC's website at
http://www.dac.com.
Registration
To register for DAC, visit http://www.dac.com or call 800-321-4573 in the U.S. to
request registration materials. The advance conference registration discount
deadline is May 10, 2004.
About DAC
DAC is the premier forum for the electronic design industry to exchange
information on products, methodologies, and processes. Attended by more than
10,000 developers, designers, researchers, managers, and engineers from
leading electronics companies and universities around the world, DAC includes
more than 200 exhibitors and offers a robust technical program covering the
electronics industry's hottest trends.
The conference is sponsored by the Association for Computing
Machinery/Special Interest Group on Design Automation (ACM/SIGDA), the
Institute of Electrical and Electronics Engineers/Circuits and Systems Society
(IEEE/CAS) and the Electronic Design Automation Consortium (EDA Consortium).
For more information, including registration, visit the DAC website at
http://www.dac.com, or contact DAC management at 800-321-4573.
Addendum
41st DAC Highlights
Business Day @ DAC
Tuesday, June 8 DAC will be taking care of business with a full day of
sessions devoted to the discussion of business issues related to the design
industry. The sessions include:
* CEO Panel: EDA: This is Serious Business (session 1)
* Panel: When IC Yield Missed the Target, Who is at Fault (session 7)
* Competitive Strategies for the Electronics Industry (session 100)
* Panel: What Happened to ASIC? Go (Recon)figure? (session 12)
* Business Models in IP, Software Licensing and Services (session 150)
"Best of ISSCC Papers" Highlights
DAC will offer a special session (session 40) with some of the best papers
from the 2004 International Solid-State Circuits Conference (ISSCC) that focus
on cutting-edge design methodology, including: "Design and Implementation of
the POWER5 Microprocessor"; "A Dual Core 64b UltraSPARC Microprocessor to
Dense Server Applications"; and "Low-Voltage-Swing Logic Circuits for a
7Ghzx86 Integer Core."
Panel Session Highlights
Eight panel sessions will offer ample debate and discussion. Panel topics
include:
* "CEO Panel: EDA: This is Serious Business" (session 1)
* "When IC Yield Misses the Target, Who Is at Fault" (session 7)
* "What Happened to ASICs? Go (Recon)figure." (session 12)
* "Verification: What Works and What Doesn't" (session 17)
* "System Level Design: Six Success Stories in Search of an Industry"
(session 22)
* "Were the Good Old Days all that Good? EDA Then and Now"
(session 32)
* "Will Moore's Law Rule in the Land of Analog" (session 37)
* "Is Statistical Timing Statistically Significant" (session 42)
Special Session Highlights
Seven special sessions in the technical program will feature invited
presentations by leading scholars and engineers. Topics cover:
* "Management of HOT Leakage" (session 2)
* "Reliable System-on-Chip Design in the Nanometer Era" (session 6)
* "The Future of Timing Closure" (session 16)
* "Platform-Based System Design" (session 26)
* "BioMEMs" (session 36)
* "Multiprocessor SoC (MPSoC) Solutions/Nightmare" (session 41)
* "Security: A New Dimension in Embedded Systems Design" (session 46)
Keynote Speakers
On Tuesday, June 8, Pat Gelsinger, Chief Technology Officer and Senior
Vice-President of Intel Corp., will examine the many-faceted EDA challenges of
continued performance increases in, "Gigascale Integration for Teraops
Performance -- Challenges, Opportunities, and New Frontiers." Then on
Thursday, June 10, Walden (Wally) C. Rhines, Chairman of the EDA Consortium
and Chief Executive Officer (CEO) of Mentor Graphics Corporation, will take an
in-depth look at the challenges most likely to be the drivers of future
industry growth, as well as some less likely possibilities in the Thursday
keynote titled, "EDA Industry Growth -- Are There Enough New Problems to
Solve?"
DAC Pavilion Panels
The DAC Pavilion will broadcast live portions of the technical program on
the exhibit floor. Pavilion-exclusive panel sessions will also offer
attendees the opportunity to participate in panel debates and relax in the
lounge. Topics include:
* EDA Business Forecast
* Wall Street Review of EDA: 2004 Update
* EDA Mergers & Acquisitions: Glory or Death?
* Export Controls in the Age of Globalization (presented by the EDA
Consortium)
* The Semiconductor IP Business in 2004
* User Forum or Useless Forums?
* Ask the CTOs: Everything You Wanted to Know But Were Afraid to Ask
* EDA Software Quality
* Does EDA Need a Roadmap for OS Support? (presented by the EDA
Consortium)
* Standards at the International Level
* IP Quality: State-of-the-Art Technical Approaches and Their Business
Impacts
* Interview with EDA's Woman of the Year
* Student Design Contest Award Presentations
* ASIC, FPGA or COT: Which Should Your Next Chip Be?
Best Paper Awards
Best Paper Awards in the amount of $1,000 each will be announced at the
keynote Thursday, June 10, in the following categories:
* Power
* Physical Circuit Design
* System-Level Design & Verification
* Logic Design & Test
* Embedded Systems
* Nanometer Analysis and Simulation
Workshops
The 41st DAC debuts a new workshop this year on UML for SoC design,
occurring Sunday, June 6. On Monday, June 7, DAC will host the "Introduction
to Chips and EDA Workshop," targeted to non-technical people. The
"Interoperability Workshop," which addresses interoperability challenges
facing the electronics industry, will take place Monday, as will the annual
"Workshop for Women in Design Automation."
Full-Day Tutorials
This year's full-day tutorial lineup includes "Getting Your 'Cool ASIC' Up
to Speed: Practical Techniques and Tools to Achieve Custom-Like Performance in
a Power-Aware Design Flow" on Monday, June 7. This tutorial will cover
techniques for balancing power and performance tradeoffs, using gain-based
delay models to achieve performance advantages and dealing with power
dissipation. Other full-day tutorials, scheduled for Friday, June 11,
include:
* Automated Macromodelling Techniques for Design of Complex Analog,
Mixed-Signal Integrated Systems
* Buffering Interconnect: From Basics To Breakthroughs
* SystemVerilog for Verification: The Unification of Design, Testbench
and Assertions in a Single Language
* Linux for Real-Time and Embedded Systems
* Silicon Debug
Hands on tutorials
Vendor-presented, hands-on tutorials will cover two areas: Power
minimization and Structured ASICs.
Power minimization
Monday
* System-Level Power Management, presented by CoWare, Inc., ChipVision
Design Systems AG, and PowerEscape, Inc.
* Low-Power Design Methodologies and Tools, presented by BullDAST
s.r.l., Accent, Inc. and STMicroelectronics
Tuesday
* Using Predictive Analysis to Guide Low Power Design Methodology,
presented by Atrenta, Inc.
Wednesday
* Flows for Power Minimization, presented by Magma Design Automation,
Inc., and Infineon Technologies
Structured ASICs
Wednesday
* Structured ASIC/Platform ASIC Design Methodology, presented by
Synplicity, Inc., LSI Logic Corp., and NEC Electronics
Thursday
* Physical Design of Structured ASICs, presented by ViASIC, Inc.
* Designing A Structured ASIC through FPGA Prototyping, presented by
Altera Corp. and Synopsys, Inc.
SOURCE 41st Design Automation Conference
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Related links:
http://www.dac.com
CONTACT:
Laura Parker, Public Relations of
Fleishman-Hillard, +1-503-402-1437, parkerl@fleishman.com, for
the 41st Design Automation Conference
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