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Prover Technology Adds Support for Equivalence Checking Advanced Synthesis Optimizations to Prover eCheck

      Prover eCheck 4.1 Enables Equivalence Checking of Advanced Design
       Transformations in ASIC, IC, and FPGA and Structured ASIC Flows

    BURLINGAME, Calif., June 2 /PRNewswire/ -- Prover(R) Technology today
announced the release of Prover(R) eCheck 4.1, a major update of the most
easy-to-use equivalence checker on the market. Prover eCheck 4.1 enables
verification of synthesis involving advanced sequential state point
optimizations such as finite state machine re-encodings, register prunes,
register merges, and register duplication, extending the scope of equivalence
checking to advanced FPGA flows.
    "The need for equivalence checking in FPGA flows has increased due to
growth in FPGA size, complexity, and use in applications where logic bugs can
have catastrophic effects," said Marcus Tallhamn, VP, Marketing and Business
Development, Prover Technology. "Prover eCheck now provides the interface
required to verify the output of FPGA synthesis tools that can forward-
annotate their sequential state point optimizations."
    Arne Boralv, CTO, Prover Technology continues, "FPGA synthesis tools
typically perform advanced sequential optimizations, whose accuracy need to be
verified. Since most equivalence checkers are tuned for ASIC flows, state
point mapping becomes problematic, and at best, requires lengthy set-up times.
With Prover eCheck 4.1, an interface for sequential state point optimizations
forward-annotated by the synthesis tool makes it possible to automate the
equivalence check, enabling robust and efficient equivalence checking in FPGA
flows."
    Other improvements in Prover eCheck 4.1 include an advanced warning and
error messages browser, lower memory consumption, and support for
unconstrained ports. Prover Technology will demo Prover eCheck in booth #4636
at the Design Automation Conference in San Diego, California, June 7th-11th.

    About Prover Technology
    Prover Technology is the world's leading provider of formal verification
solutions for Electronic Design Automation, Railway Interlocking Systems and
Embedded Systems. Its Prover Plug-In proof engine products are used in more
than ten tools for verifying functional equivalence, specifications,
assertions and consistency. Founded in 1989, Prover Technology is the most
experienced company in the field of automated formal verification. Prover
Technology has offices in Silicon Valley, France, and Sweden (HQ). For more
information and office locations, visit Prover Technology's web site at
http://www.prover.com .

    About Prover eCheck
    Prover eCheck is a high capacity equivalence checker that enables SoC,
ASIC and FPGA developers to verify that design functionality is preserved
through complex design transformations. State of the art formal proof engines
enable Prover eCheck users to get functional closure on multi-million gate
designs in minutes or hours. Prover eCheck pricing starts at $40k for a
node-locked 1-year TBL. More information is available at
http://www.prover.com/products/eda/echeck.xml .

    NOTE:  All products are the trademarks, service marks, or registered
trademarks of their respective holder.

    Contact:

     Marcus Tallhamn, Prover Technology,
     650-722-2750
     marcus@prover.com


SOURCE Prover Technology




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Related links:
  • http://www.prover.com
    CONTACT:
    Marcus Tallhamn of Prover Technology,
    +1-650-722-2750, or marcus@prover.com