SAN JOSE, Calif., June 7 /PRNewswire-FirstCall/ --
What: If you are going to be attending DAC this week, you won't want
to miss the ASIC, COT or FPGA: Which Should Your Next Chip Be?
panel, which will take place Thursday, June 10, from
10:15 a.m. to 11 a.m. in the DAC Pavilion on the exhibit floor.
Altera will be represented on this panel by Robert Blake, vice
president of product planning. Blake will compare and contrast
the design costs and challenges involved in implementing
designs in FPGAs and ASICs. In addition, Altera (Nasdaq: ALTR)
will be conducting joint product demonstrations and
presentations in the booths of a number of its EDA partners,
including Cadence, Celoxica, Mentor, Synopsys and Synplicity.
These demonstrations will highlight the benefits engineers can
gain from using the tools of these leading EDA vendors to
implement their designs in Altera FPGAs. We look forward to
seeing you at DAC.
Speaker: Robert Blake, Vice President, Product Planning, Altera
When: Panel: ASIC, COT, or FPGA: Which Should Your Next Chip Be?
Thursday, June 10
10:15 a.m.-11:00 a.m.
Room: DAC Pavilion, Exhibit Floor
Where: DAC 2004
June 7-11, 2004
San Diego Convention Center
111 W Harbor Dr
San Diego, CA 92101
Contact: Bruce Fienberg
Altera Corporation
408-544-6397
newsroom@altera.com
For additional information, please visit: http://www.dac.com/41st/index.html.
NOTE: Altera, The Programmable Solutions Company, the stylized Altera
logo, specific device designations, and all other words that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks
and service marks of Altera Corporation in the U.S. and other countries. All
other product or service names are the property of their respective holder.
SOURCE Altera Corporation
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Related links:
http://www.altera.com
CONTACT:
Bruce Fienberg of Altera Corporation,
+1-408-544-6397, or newsroom@altera.com
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